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Blue Pearl Software: Validating Timing Constraints in FPGAs
Bill Alexander, Vice President of Marketing at Blue Pearl Software, discusses their FPGA timing constraint technology.
Blue Pearl Software has 3 products that are integrated into a single executable that allows designers of ASICs and FPGAs to improve their productivity and reduce design time.
Indigo RTL Analysis is a functional analysis and linting tool that parses RTL descriptions to provide valuable feedback on potential errors for both the design and the design flow.
Indigo helps designers write correct RTL quicker.
Cobalt Timing Constraint Generation generates SDC timing constraints from the RTL description to provide the designer with a comprehensive set of accurate constraints to enable faster timing closure.
Cobalt saves designers a huge amount of time writing timing constraints and the comprehensive SDC file generated achieves faster implementation of a correct chip.
Azure Timing Constraint Validation reads in the RTL description and the SDC file for that design to automatically validate the timing constraints which significantly lowers the risk to implement a digital design.
Azure saves designers a lot of time checking whether they have a correct SDC to use for chip implementation.
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About Blue Pearl Software
Provides innovative, high performance tools that generate accurate timing exception constraints automatically, before synthesis, validate existing timing exceptions and find functional problems in RTL code.
Cobalt Timing Constraint Generation enables faster timing closure for complex chips.
Designers using Blue Pearl's solutions improve the quality of results, save time and, lower the cost of their chip...
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