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> fpga interview: aldec, inc.: acitve-hdl 8.1 & new verification technologies
Aldec, Inc.: Active-HDL 8.1 & New Verification Technologies
Lori Nguyen, Director of Marketing, Aldec, discusses Active-HDL 8.1, which also includes enhanced support for VHDL 2008 (IEEE Standard P1076-2008) including new constructs and libraries.
The new release supports new and updated libraries including: Assertions, OVL 2.2 and VTL. A new DPI-wizard to help create quick interfaces between SystemVerilog and C applications is now included in Active-HDL 8.1. The DPI-wizard allows simple entry of C/C++ tasks and functions and generates C wrappers, and sample SystemVerilog files.
The wizard also creates a configuration file for compiling generated C files into a dynamic-link library.
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About Aldec
Industry-leader in electronic design and offers a patented technology suite including: design entry, HDL simulators, hardware-assisted verification, design rule checking, co-simulation, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions.
Aldec tools handle: Verilog, SystemVerilog, VHDL, SystemC, Assertions, ultra-fast debugging, code coverage and linting. [FPGA, ASIC, CPLD]
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